1. Field of the Invention
The present invention generally relates to packages for integrated circuit (IC) chips and, more particularly, to a new lead frame for IC memory packages that minimizes the inductance in the power distribution network.
2. Description of the Prior Art
FIG. 1A shows a conventional A-wire lead frame 10 for a dynamic random access memory (DRAM) IC module 12. The lead frame 10 includes a plurality of signal leads 14 and two power bus leads 16 and 18 respectively connected to voltages V.sub.cc and V.sub.ss, the latter typically being circuit ground. FIG. 1B is an end view of the DRAM module 12 showing how the A-wire lead frame 10 is attached to the top surface of the chip 20 and electrically joined to the chip signal and power pads 22 by wire bonds 24. As shown in FIG. 1B, the leads 14, 16, and 18 can be formed either as a J-lead or a gullwing lead for surface mounting on a printed circuit board (PCB).
Memory modules in the form of IC packages are conventionally mounted on PCBs in an array. In order to conserve board area, it is sometimes necessary to stack memory modules as shown in FIG. 2. In FIG. 2, a first DRAM module 26 is surface mounted to a PCB 28 and supports a second DRAM module 30. The leads 32 of the second DRAM module 30 overlap and are bonded to the leads 34 of the first DRAM module 26 forming an electrical connection therewith.
The A-wire lead frames used in the conventional IC modules shown in FIGS. 1 and 2 have a power distribution design as shown in FIG. 3A. This figure is similar to FIG. 1A but omits the signal leads and shows only the power buses 16 and 18 for the sake of clarity. As can be seen in FIG. 3A, there are several current loops for the current I.sub.cc flowing from the voltage source V.sub.cc to the voltage sink V.sub.cc. However, by stacking memory modules, there is a very large inductive loop between the power buses causing high power supply noise, especially when more than two modules are stacked. This is best shown in FIG. 3B for a four module stack comprising modules 36, 38, 40, and 42. As can be seen in FIG. 3B, there is an increased inductance due to the power distribution to the top module 42, as indicated by the arrows for the I.sub.cc current path to chip and return. The noise is caused by the demand for current by the top module 42 when it becomes active. The high inductance in the circuit causes ringing on the V.sub.cc and V.sub.ss power distribution buses which adversely affect the voltage tolerance of the selected chip and can result in data integrity problems.
U.S. Pat. No. 4,862,245 to Pashby et al. discloses a package for an IC chip. The Pashby et al. patent is instructive for its explanation of the basic A-wire lead frame technology. In particular, Pashby et al. show power the bus bars for the A-wire lead frame. The power bus bars in this technology diverge away from each other at both ends and protrude from different sides of the package. This construction has a disadvantage of maximizing the flux linkage for a given current. As a result, the inductance of the lead frame is maximized except above the chip where the two power buses run parallel and close together and, as stated in the Pashby et al. patent, the wire bond leads to the chip power pads are shorter than in non-A-wire packages.
U.S. Pat. No. 4,965,654 to Karner et al. shows ground planes between the lead frame and the chip. These ground planes, however, have no effect on the power line inductance because the planes are separately connected to ground and high voltage and are not part of the current return path. The main function of the metal planes in the Karner et al. package are to provide shielding between signal lines and chip and to reduce coupling between adjacent lines by increasing signal capacitance to the shield planes.
U.S. Pat. No. 4,916,519 to Ward discloses an IC package using an A-wire lead frame. Ward shows how to reduce a long wire-bond connection from the lead frame to the chip by making two shorter bond connections between specially placed A-wire leads and the chip. Ward does not, however, address the problem of inductive coupling between stacked IC memory modules.